Texas Instruments TMS570LC4357

www.ti.com
8
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Contents
11.4.2 MPU Lock Register (MPULOCK)............................................................................. 472
11.4.3 MPU Diagnostics Control Register (MPUDIAGCTRL)..................................................... 473
11.4.4 MPU Diagnostic Address Register (MPUDIAGADDR) .................................................... 474
11.4.5 MPU Error Status Register (MPUERRSTAT)............................................................... 474
11.4.6 MPU Error Address Register (MPUERRADDR)............................................................ 476
11.4.7 MPU Control Register 1 (MPUCTRL1) ...................................................................... 476
11.4.8 MPU Control Register 2 (MPUCTRL2) ...................................................................... 477
11.4.9 MPU Type Register (MPUTYPE)............................................................................. 478
11.4.10 MPU Region Base Address Register (MPUREGBASE) ................................................. 479
11.4.11 MPU Region Size and Enable Register (MPUREGSENA) .............................................. 479
11.4.12 MPU Region Access Control Register (MPUREGACR) ................................................. 481
11.4.13 MPU Region Number Register (MPUREGNUM) ......................................................... 482
12 Error Profiling Controller (EPC) .......................................................................................... 483
12.1 Overview ................................................................................................................... 484
12.2 Module Operation......................................................................................................... 484
12.2.1 Uncorrectable Fault Operation................................................................................ 485
12.2.2 Correctable Fault Operation................................................................................... 485
12.3 How to Use EPC.......................................................................................................... 487
12.3.1 Functional Mode ................................................................................................ 487
12.3.2 CAM Diagnostic Mode ......................................................................................... 488
12.4 EPC Control Registers ................................................................................................... 488
12.4.1 EPC REVID Register (EPCREVID) .......................................................................... 489
12.4.2 EPC Control Register (EPCCNTRL) ......................................................................... 490
12.4.3 Uncorrectable Error Status Register (UERRSTAT) ........................................................ 491
12.4.4 EPC Error Status Register (EPCERRSTAT)................................................................ 492
12.4.5 FIFO Full Status Register (FIFOFULLSTAT) ............................................................... 493
12.4.6 IP Interface FIFO Overflow Status Register (OVRFLWSTAT)............................................ 494
12.4.7 CAM Index Available Status Register (CAMAVAILSTAT)................................................. 494
12.4.8 Uncorrectable Error Address Register n (UERR_ADDR) ................................................. 495
12.4.9 CAM Content Update Register n (CAM_CONTENT) ...................................................... 495
12.4.10 CAM Index Registers (CAM_INDEX[0-7]) ................................................................. 496
13 CPU Compare Module for Cortex-R5F (CCM-R5F)................................................................. 497
13.1 Overview ................................................................................................................... 498
13.1.1 Main Features................................................................................................... 498
13.1.2 Block Diagram................................................................................................... 498
13.2 Module Operation......................................................................................................... 499
13.2.1 CPU/VIM Output Compare Diagnostic....................................................................... 500
13.2.2 CPU Input Inversion Diagnostic............................................................................... 504
13.2.3 Checker CPU Inactivity Monitor............................................................................... 505
13.2.4 Power Domain Inactivity Monitor ............................................................................. 507
13.2.5 Operation During CPU Debug Mode......................................................................... 507
13.3 Control Registers ......................................................................................................... 507
13.3.1 CCM-R5F Status Register 1 (CCMSR1) .................................................................... 508
13.3.2 CCM-R5F Key Register 1 (CCMKEYR1).................................................................... 509
13.3.3 CCM-R5F Status Register 2 (CCMSR2) .................................................................... 510
13.3.4 CCM-R5F Key Register 2 (CCMKEYR2).................................................................... 511
13.3.5 CCM-R5F Status Register 3 (CCMSR3) .................................................................... 512
13.3.6 CCM-R5F Key Register 3 (CCMKEYR3).................................................................... 513
13.3.7 CCM-R5F Polarity Control Register (CCMPOLCNTRL)................................................... 513
13.3.8 CCM-R5F Status Register 4 (CCMSR4) .................................................................... 514
13.3.9 CCM-R5F Key Register 4 (CCMKEYR4).................................................................... 515
13.3.10 CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0) ......................................... 516
14 Oscillator and PLL ............................................................................................................ 517