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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
14.1 Introduction ................................................................................................................ 518
14.1.1 Features.......................................................................................................... 518
14.2 Quick Start................................................................................................................. 519
14.3 Oscillator ................................................................................................................... 520
14.3.1 Oscillator Implementation...................................................................................... 521
14.3.2 Oscillator Enable................................................................................................ 521
14.3.3 Oscillator Disable ............................................................................................... 521
14.4 Low Power Oscillator and Clock Detect (LPOCLKDET)............................................................. 522
14.4.1 Clock Detect..................................................................................................... 522
14.4.2 Behavior on Oscillator Failure................................................................................. 522
14.4.3 Recovery from Oscillator Failure ............................................................................. 523
14.4.4 LPOCLKDET Enable........................................................................................... 523
14.4.5 LPOCLKDET Disable .......................................................................................... 524
14.4.6 Trimming the HF LPO Oscillator.............................................................................. 524
14.5 PLL ......................................................................................................................... 525
14.5.1 Modulation ....................................................................................................... 527
14.5.2 PLL Output Control ............................................................................................. 528
14.5.3 Behavior on PLL Fail ........................................................................................... 531
14.5.4 Recovery from a PLL Failure.................................................................................. 532
14.5.5 PLL Modulation Depth Measurement ........................................................................ 533
14.5.6 PLL Frequency Measurement Circuit ........................................................................ 533
14.5.7 PLL2.............................................................................................................. 533
14.6 PLL Control Registers.................................................................................................... 534
14.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)..................................... 535
14.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)............................................................ 536
14.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)............................................................ 537
14.7 Phase-Locked Loop Theory of Operation ............................................................................. 538
14.7.1 Phase-Frequency Detector.................................................................................... 538
14.7.2 Charge Pump and Loop Filter................................................................................. 539
14.7.3 Voltage-Controlled Oscillator.................................................................................. 539
14.7.4 Frequency Modulation ......................................................................................... 540
14.8 Programming Example................................................................................................... 540
15 Dual-Clock Comparator (DCC) Module ................................................................................ 542
15.1 Introduction ................................................................................................................ 543
15.1.1 Main Features................................................................................................... 543
15.1.2 Block Diagram................................................................................................... 543
15.2 Module Operation......................................................................................................... 544
15.2.1 Continuous Monitoring Mode.................................................................................. 544
15.2.2 Single-Shot Measurement Mode ............................................................................. 547
15.3 Clock Source Selection for Counter0 and Counter1 ................................................................. 548
15.4 DCC Control Registers................................................................................................... 549
15.4.1 DCC Global Control Register (DCCGCTRL) ............................................................... 550
15.4.2 DCC Revision Id Register (DCCREV) ...................................................................... 551
15.4.3 DCC Counter0 Seed Register (DCCCNT0SEED) ......................................................... 551
15.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) .......................................................... 552
15.4.5 DCC Counter1 Seed Register (DCCCNT1SEED) ......................................................... 552
15.4.6 DCC Status Register (DCCSTAT) ........................................................................... 553
15.4.7 DCC Counter0 Value Register (DCCCNT0) ................................................................ 554
15.4.8 DCC Valid0 Value Register (DCCVALID0) ................................................................. 555
15.4.9 DCC Counter1 Value Register (DCCCNT1) ................................................................ 555
15.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) .............................. 556
15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) .............................. 557
16 Error Signaling Module (ESM) ............................................................................................ 558