Texas Instruments TMS570LC4357 - Page 10

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10
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
16.1 Overview ................................................................................................................... 559
16.1.1 Feature List...................................................................................................... 559
16.1.2 Block Diagram................................................................................................... 559
16.2 Module Operation......................................................................................................... 561
16.2.1 Reset Behavior.................................................................................................. 561
16.2.2 ERROR Pin Timing............................................................................................. 562
16.2.3 Forcing an Error Condition .................................................................................... 563
16.3 Recommended Programming Procedure.............................................................................. 564
16.4 ESM Control Registers................................................................................................... 565
16.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)............................... 566
16.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1).............................. 566
16.4.3 ESM Interrupt Enable Set/Status Register 1 (ESMIESR1)................................................ 567
16.4.4 ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) ............................................. 567
16.4.5 ESM Interrupt Level Set/Status Register 1 (ESMILSR1).................................................. 568
16.4.6 ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) ............................................... 568
16.4.7 ESM Status Register 1 (ESMSR1) ........................................................................... 569
16.4.8 ESM Status Register 2 (ESMSR2) ........................................................................... 569
16.4.9 ESM Status Register 3 (ESMSR3) ........................................................................... 570
16.4.10 ESM ERROR Pin Status Register (ESMEPSR) .......................................................... 570
16.4.11 ESM Interrupt Offset High Register (ESMIOFFHR) ...................................................... 571
16.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR) ....................................................... 572
16.4.13 ESM Low-Time Counter Register (ESMLTCR) ........................................................... 573
16.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)................................................ 573
16.4.15 ESM Error Key Register (ESMEKR)........................................................................ 574
16.4.16 ESM Status Shadow Register 2 (ESMSSR2) ............................................................. 574
16.4.17 ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) ..................................... 575
16.4.18 ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) .................................. 575
16.4.19 ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) ............................................. 576
16.4.20 ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4) ........................................... 576
16.4.21 ESM Interrupt Level Set/Status Register 4 (ESMILSR4) ................................................ 577
16.4.22 ESM Interrupt Level Clear/Status Register 4 (ESMILCR4) ............................................. 577
16.4.23 ESM Status Register 4 (ESMSR4) ......................................................................... 578
16.4.24 ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) ..................................... 579
16.4.25 ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) .................................. 579
16.4.26 ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) ............................................. 580
16.4.27 ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) ........................................... 580
16.4.28 ESM Interrupt Level Set/Status Register 7 (ESMILSR7) ................................................ 581
16.4.29 ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) ............................................. 581
16.4.30 ESM Status Register 7 (ESMSR7) ......................................................................... 582
17 Real-Time Interrupt (RTI) Module ........................................................................................ 583
17.1 Overview ................................................................................................................... 584
17.1.1 Features.......................................................................................................... 584
17.1.2 Industry Standard Compliance Statement................................................................... 584
17.2 Module Operation......................................................................................................... 585
17.2.1 Counter Operation.............................................................................................. 585
17.2.2 Interrupt/DMA Requests ....................................................................................... 587
17.2.3 RTI Clocking..................................................................................................... 588
17.2.4 Synchronizing Timer Events to Network Time (NTU)...................................................... 588
17.2.5 Digital Watchdog (DWD)....................................................................................... 591
17.2.6 Low Power Modes.............................................................................................. 594
17.2.7 Halting Debug Mode Behaviour............................................................................... 594
17.3 RTI Control Registers .................................................................................................... 595
17.3.1 RTI Global Control Register (RTIGCTRL)................................................................... 596