PLL
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SPNU563A–March 2018
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Oscillator and PLL
14.5.2.5 Summary of PLL Timings
In addition to controlling the lock period and disabling the clock during an ODPLL change, the PLL also
generates reset delays. When power-on reset is released (nPORRST 0 --> 1), that release is delayed by
1024 OSCIN cycles so that it is released at the same time that the oscillator valid is asserted. The system
reset release is delayed by an additional 8 oscillator clock cycles.
Table 14-3. Summary of PLL Timings
Parameter Value
nPORRST delay T
nPORRST
= 1024 x T
OSCIN
nRST delay T
nRST
= 1032 x T
OSCIN
OSC valid T
OSCVALID
= 1024 x T
OSCIN
Lock T
Lock
= (512 x T
OSCIN
) + (1024 x NR x T
OSCIN
)
Enable clocks after lock T
Enable
= 6 x T
OSCIN
Disable clocks after lock T
Enable
= 150 x T
OSCIN
Change ODPLL T
ODPLL
= 3 x T
OSCIN
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