time
CPU
DWD
Down
Counter
access
to DWD
0
0x1FFFFFF
Preload
Register
Value left
set DWD
Preload
enable
DWD
write E51A
to WDKEY
write A35C
to WDKEY
write A35C
to WDKEY
write E51A
to WDKEY
Reset/NMI
shifted 13bits
Module Operation
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SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.2.5.1 Digital Watchdog (DWD)
The DWD is disabled by default. If it should be used, it must be enabled by writing a 32-bit value to the
RTIDWDCTRL register.
NOTE: Once the DWD is enabled, it cannot be disabled except by system reset or power on reset.
If the correct key sequence is written to the RTIWDKEY register (0xE51A followed by 0xA35C), the 25-bit
DWD down counter is reloaded with the left justified 12-bit preload value stored in RTIDWDPRLD. If an
incorrect value is written, a watchdog reset or NMI will occur immediately. A reset or NMI will also be
generated when the DWD down counter is decremented to 0.
While the device is in suspend mode (halting debug mode), the DWD down counter keeps the value it had
when entering suspend mode.
The DWD down counter will be decremented with the RTICLK frequency.
Figure 17-9. DWD Operation
The expiration time of the DWD down counter can be determined with the following equation:
texp = (DWDPRLD + 1) × 2
13
/RTICLK
where
DWDPRLD = 0...4095
NOTE: Care should be taken to ensure that the CPU write to the watchdog register is made allowing
time for the write to propagate to the RTI.
17.2.5.2 Digital Windowed Watchdog (DWWD)
In addition to the time-out boundary configurable via the digital watchdog discussed in Section 17.2.5.1,
for enhanced safety metrics it is desirable to check for a watchdog "pet" within a time window rather than
using a single time threshold. This is enabled by the digital windowed watchdog (DWWD) feature.
• Functional Behavior
The DWWD opens a configurable time window in which the watchdog must be serviced. Any attempt to
service the watchdog outside this time window, or a failure to service the watchdog in this time window,
will cause the watchdog to generate either a reset or a NMI to the CPU. This is controlled by configuring
the RTIWWDRXNCTRL register. As with the DWD, the DWWD is disabled after power on reset. When the
DWWD is configured to generate a non-maskable interrupt on a window violation, the watchdog counter
continues to count down. The NMI handler needs to clear the watchdog violation status flag(s) and then
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