Overview
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SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.1 Overview
The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into CRC controller. The responsibility of CRC controller is to calculate
the signature for a set of data and then compare the calculated signature value against a pre-determined
good signature value. CRC controller supports two channels to perform CRC calculation on multiple
memories in parallel and can be used on any memory system.
18.1.1 Features
The CRC controller offers:
• Two channels to perform background signature verification on any memory sub-system.
• Data compression on 8, 16, 32, and 64 bit data size.
• Maximum-length PSA (Parallel Signature Analysis) register constructed based on 64 bit primitive
polynomial.
• Each channel has a CRC Value Register that contains the pre-determined CRC value.
• Use timed base event trigger from timer to initiate DMA data transfer.
• Programmable 20-bit pattern counter per channel to count the number of data patterns for
compression.
• Three modes of operation. Auto, Semi-CPU and Full-CPU.
• For each channel, CRC can be performed either by CRC Controller or by CPU.
• Automatically perform signature verification without CPU intervention in AUTO mode.
• Generate interrupt to CPU in Semi-CPU mode to allow CPU to perform signature verification itself.
• Generate CRC fail interrupt in AUTO mode if signature verification fails.
• Generate Timeout interrupt if CRC is not performed within the time limit.
• Generate DMA request per channel to initiate CRC value transfer.
18.1.2 Block Diagram
Figure 18-1 shows a block diagram of the CRC controller.
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