Texas Instruments TMS570LC4357

www.ti.com CRC Control Registers
645
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Cyclic Redundancy Check (CRC) Controller Module
Table 18-8. CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions (continued)
Bit Field Value Description
8 CH2_CCITENS Channel 2 Compression Complete Interrupt Enable Bit.
User and Privileged mode (read):
0 Compression Complete Interrupt is disabled.
1 Compression Complete Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Compression Complete Interrupt is enabled.
7-5 Reserved 0 Reads return 0. Writes have no effect.
4 CH1_TIMEOUTENS Channel 1 Timeout Interrupt Enable Bit.
User and Privileged mode (read):
0 Timeout Interrupt is disabled.
1 Timeout Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Timeout Interrupt is enabled.
3 CH1_UNDERENS Channel 1 Underrun Interrupt Enable Bit.
User and Privileged mode (read):
0 Underrun Interrupt is disabled.
1 Underrun Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Underrun Interrupt is enabled.
2 CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit.
User and Privileged mode (read):
0 Overrun Interrupt is disabled.
1 Overrun Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Overrun Interrupt is enabled.
1 CH1_CRCFAILENS Channel 1 CRC Compare Fail Interrupt Enable Bit.
User and Privileged mode (read):
0 CRC Fail Interrupt is disabled.
1 CRC Fail Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 CRC Fail Interrupt is enabled.
0 CH1_CCITENS Channel 1 Compression Complete Interrupt Enable Bit.
User and Privileged mode (read):
0 Compression Complete Interrupt is disabled.
1 Compression Complete Interrupt is enabled.
Privileged mode (write):
0 No effect.
1 Compression Complete Interrupt is enabled.