3FF
R
Vin
V(cal1)
V(cal1) = [VREFHI*R1+VREFLO*R2] / (R1 + R2)
V(cal2) = [VREFLO*R1+VREFHI*R2] / (R1 + R2)
[V(cal1) + V(cal2)] / 2 = (VrefHi-VrefLo) / 2
Digital Code (hex)
D(cal1)
D(cal)
D(cal2)
[D(cal1) + D(cal2)] / 2 = D(cal)
*Real
10-bit ADC’s Theoretical
Transfer Function
VrefHi
VrefLo
V(cal2)
* The Real function shown is a straight
line between the ends points of the real
staircase characteristic.
The Theoretical transfer function is
for reference only.
straight line
Transfer Function
CPU
MEMORY
D(cal1)
D(cal2)
(VrefHi - VrefLo)/2
FS
Basic Operation
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SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
Figure 22-14. Mid-point Value Calculation
22.2.6.2 ADC Self-Test Mode
The ADC module supports a self-test mode which can be used to detect an open or a short on the ADC
input channels. Self-test mode is enabled by setting the SELF_TEST bit (ADCALCR.24). Any conversion
type (continuous or single conversion, freeze enabled or non-freeze enabled, interrupts enabled or
disabled) can be performed in this mode.
In normal mode, setting the self-test mode while a conversion sequence is in process can corrupt the
current channel conversion results. However, the next channel in the sequence is converted correctly
during the additional self-test cycle. The logic associated with both self-test and calibration is shown in
Figure 22-15.
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