Infineon Technologies TC1796 User Manual

TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-186 V2.0, 2007-07
GPTA, V2.0
REN 3rwRequest Enable
0
B
Service request is disabled.
1
B
Service request SQSk is activated when a
- capture event has occurred
- compare event has occurred
- timer overflow has happened
depending on the operation mode selected by bit
field MOD.
SOL 4rwCompare Mode: Select Output Low
0
B
Compare is deactivated or on high level.
1
B
Compare operation is enabled by a low level on
select input SI
1)
.
SOH 5rwCompare Mode: Select Output High
0
B
Compare is deactivated or on high level.
1
B
Compare operation is enabled by a high level on
select input SI
1)
.
BYP 6rwBypass
0
B
M0O/M1O lines are affected either by M0I/M1I
lines or by OCM0/OCM1 bits.
1
B
M0O/M1O lines are affected only by M0I/M1I
lines.
This bit is cleared if mode is switched to Timer Mode.
OCM2 must be set in any case to enable reaction on
M0I/M1I change.
EOA 7rwhEnable On Action
0
B
LTCk is enabled for local events.
1
B
LTCk is disabled for local events. On an event on
the communication link via M0I/M1I lines, EOA
will be cleared and local events will be enabled.
EOA is bit protected (see Section 24.3.2). EOA is
cleared if mode is switched to Timer Mode.
ILM 8rwInput Line Mode
0
B
Input line is operating in Edge Sensitive Mode.
1
B
Input line is operating in Level Sensitive Mode.
In case of full speed GPTA module clock selection as
input clock, Level Sensitive Mode must be selected. In
this case the Edge Sensitive Mode will not produce any
event.
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English