Infineon Technologies TC1796 - Page 2118

User’s Manual L-2 V2.0, 2007-07
TC1796
System and Peripheral Units (Vol. 1 and 2)
Keyword Index
Baud rate generation 19-12 [2]–
19-16 [2]
Asynchronous modes 19-13 [2]
Synchronous mode 19-16 [2]
Block diagram
Asynchronous modes 19-4 [2]
Synchronous mode 19-9 [2]
DMA request outputs 19-42 [2]
Error detection 19-17 [2]
Features 19-2 [2]
Interrupt generation 19-17 [2]
Module implementation 19-30 [2]–??
DMA request outputs 19-42 [2]
Input/output function selection
19-36 [2]
Pad output driver characteristics
selection 19-39 [2]
Registers 19-19 [2]–19-29 [2]
BG 19-27 [2]
CON 19-22 [2]
FDV 19-27 [2]
ID 19-20 [2]
Offset addresses 19-19 [2]
Overview 19-19 [2]
PISEL 19-21 [2]
RBUF 19-29 [2]
TBUF 19-28 [2]
WHBCON 19-25 [2]
Synchronous mode 19-9 [2]–19-11 [2]
Timings 19-11 [2]
B
BCU
LBCU
Offset addresses 6-7 [1]
SBCU
Offset addresses 6-34 [1]
BCUs
DBCU and PBCU 6-5 [1]
Bus agents and priorities 6-5 [1]
Error handling 6-6 [1]
Operation 6-5 [1]
Registers 6-7 [1]
SBCU and RBCU 6-24 [1]
Bus agents and priorities 6-24 [1]
Bus arbitration 6-24 [1]
Bus error handling 6-25 [1]
Registers 6-34 [1]
Starvation prevention 6-25 [1]
Boot 4-12 [1]
Normal boot 4-14 [1]
Scheme 4-12 [1]
Selection table 4-12 [1]
Boot ROM 4-16 [1]
Alternate Boot Mode 4-28 [1]
Program Structure 4-16 [1]
C
CAN
Address map 22-214 [2]
Basics 22-2 [2]
Addressing and arbitration 22-2 [2]
Basic-/Full-CAN 22-10 [2]
Error detection and handling
22-9 [2]
Frame formats 22-3 [2]
Nominal bit time 22-8 [2]
Block diagram 22-14 [2]
DMA requests 22-209 [2]
Module implementation 22-199 [2]–
22-212 [2]
External registers 22-200 [2]
I/O line control 22-205 [2]
Input/output function selection
22-205 [2]
Interfaces 22-199 [2]
Interrupt control 22-210 [2]
Module clock generation 22-201 [2]
MultiCAN
Bit timing 22-24 [2]
Block diagram 22-18 [2]
Clock generation 22-21 [2]
Interrupt structure 22-20 [2]
Message acceptance filtering
22-37 [2]
Message object data handling