TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-80 V2.0, 2007-07
DMA, V2.0
The Channel Status Register contains the current transfer count and a pattern detection
compare result.
DMA_CHSR0x (x = 0-7)
DMA Channel 0x Status Register
(x*20
H
+80
H
) Reset Value: 0000 0000
H
DMA_CHSR1x (x = 0-7)
DMA Channel 1x Status Register
(x*20
H
+180
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
LXO 0 TCOUNT
rh r rh
Field Bits Type Description
TCOUNT [8:0] rh Transfer Count Status
TCOUNT holds the actual value of the DMA transfer
count for DMA channel mx. TCOUNT is loaded with
the value of CHCRmx.TREL when TRSR.CHmx
becomes set (and TCOUNT = 0). After each DMA
transfer, TCOUNT is decremented by 1.
LXO 15 rh Old Value of Pattern Detection
This bit contains the compare result of a pattern
compare operation when 8-bit or 16-bit data width is
selected.
8-bit data width: see Table 12-2 and Figure 12-25
16-bit data width: see Table 12-3 and Figure 12-26
0
B
The corresponding pattern compare operation
didn’t found a pattern match at the last move.
1
B
The corresponding pattern compare operation
found a pattern match at the last move.
0 [14:9],
[31:16]
r Reserved
Read as 0; should be written with 0.
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