Infineon Technologies TC1796 - Page 992

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-3 V2.0, 2007-07
Regs, V2.0
Port 5 F000 1100
H
-
F000 11FF
H
see
Page 18-27
256 byte
Port 6 F000 1200
H
-
F000 12FF
H
see
Page 18-28
256 byte
Port 7 F000 1300
H
-
F000 13FF
H
see
Page 18-29
256 byte
Port 8 F000 1400
H
-
F000 14FF
H
see
Page 18-30
256 byte
Port 9 F000 1500
H
-
F000 15FF
H
see
Page 18-31
256 byte
Port 10 F000 1600
H
-
F000 16FF
H
see
Page 18-32
256 byte
Reserved F000 1700
H
-
F000 17FF
H
BE BE –
General Purpose Timer Array 0 (GPTA0) F000 1800
H
-
F000 1FFF
H
see
Page 18-33
8 × 256
byte
General Purpose Timer Array 1 (GPTA1) F000 2000
H
-
F000 27FF
H
see
Page 18-42
8 × 256
byte
Local Timer Cell Array 2 (LTCA2) F000 2800
H
-
F000 2FFF
H
see
Page 18-50
8 × 256
byte
Reserved F000 3000
H
-
F000 3BFF
H
BE BE –
Direct Memory Access Controller (DMA) F000 3C00
H
-
F000 3EFF
H
see
Page 18-53
3 × 256
byte
Reserved F000 3F00
H
-
F000 3FFF
H
BE BE –
MultiCAN Controller (CAN) F000 4000
H
-
F000 5FFF
H
see
Page 18-65
8 Kbyte
Reserved F000 6000
H
-
F003 FFFF
H
BE BE –
PCP Reserved F004 0000
H
-
F004 3EFF
H
BE BE –
Table 18-2 Block Address Map of Segment 15 (cont’d)
Unit Address
Range
Access Mode Size
Read Write