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Instruction Set
1095
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
Cycles One
Register modified Register A, B, R, S or T if selected
Description ECMP can use all pins. This instruction compares a 25-bit data value stored in
the data field (D31–D7) to the value stored in the selected ALU register (A, B,
R, S, or T). Register select encoding can be found in Section 23.6.2.
If R, S, or T registers are selected, and if the 25-bit data field matches, ECMP
updates the register with the 32-bit value (D31-D0).
If the hr_lr bit is cleared, the pin action will occur after a high resolution delay
from the next loop resolution clock. If the hr_lr bit is set, the delay is ignored.
This delay is programmed in the data field (D6–D0).
The behavior of the pins is governed by the four action options in bits C4:C3.
ECMP uses the zero flag to generate opposite pin action (synchronized to the
loop resolution clock).
angle_comp Determines if an angle compare is performed. A value of ON causes
the comparison to be performed only if the new angle flag is set (NAF
= 1). If OFF is specified, the compare is then performed regardless of
the state of the new angle flag.
Default: OFF.
irq Specifies whether or not an interrupt is generated. A value of ON
sends an interrupt if register and data field values are equivalent. If
OFF is selected, no interrupt is generated.
Default: OFF.
data Specifies the value for the data field. This value is compared with the
selected register.
hr_data Specifies the HR delay.
Default: 0.
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