Memory View for DCP-1A/B
Increasing Address
Buffer 1A
Increasing Address
Buffer 1A
Buffer 1B
Switch
t1
TU request (1) X X X X
Element Counter 1A 5 4 3 2 1 5 4 3 2 1
Element Counter 1B 5 4 3 2 1 5 4 3 2 1
Element Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TU request (2) X X X X
Element Counter 2A 5 4 3 2 1 5 4 3 2 1
Element Counter 2B 5 4 3 2 1 5 4 3 2 1
Element Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
t2 t3
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Module Operation
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SPNU563A–March 2018
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High-End Timer Transfer Unit (HTU) Module
24.2.1.3 Dual Buffer Implementation
The transfer unit provides double control packets (DCPs) supporting the use of two buffers per data
stream (per HTU request source). If one buffer should be read by the CPU or DMA, the data stream is
directed to the other buffer and the first buffer is frozen. Switching to the other buffer can be triggered with
a write access to the CPENA register or with the DCP configured to automatically switch to the other
buffer when the programmed number of frames has been transmitted. Freezing the buffer avoids this
buffer to be overwritten with new HET data while the CPU or DMA reads this buffer.
Figure 24-6 shows a timing example of two HET instructions 1 and 2, which are the request sources for
the HTU (and are controlled by DCP 1 and DCP 2). Each generated frame has 5 element transfers.
Request source 1 has two RAM buffers, controlled by two control packets 1A and 1B. Request source 2
has two RAM buffers, controlled by two control packets 2A and 2B.
Figure 24-6. Dual Buffer Timing
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