Use Cases
www.ti.com
1146
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
High-End Timer Transfer Unit (HTU) Module
32-Bit-Transfer of data fields:
Table 24-6 shows how the internal element counter, frame counter and the address registers change over
time for the example described above. Every time the PCNT instruction captures a new value it generates
a request to the HTU, which starts a frame. At the end of each frame the frame counter decrements.
(1)
Shows the byte addresses
Table 24-6. 32-Bit-Transfer of Data Fields
(1)
Frame Counter 3 2 1
Element Counter 3 2 1 3 2 1 3 2 1
Source Address (HET) 38h 48h 58h 38h 48h 58h 38h 48h 58h
Destination Address (main CPU RAM) 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h
The destination buffer is filled with the WCAP, ECNT, and PCNT data field values as shown in Table 24-7.
Table 24-7. Destination Buffer Values
Address Frame Count Instruction Value
70h 3 WCAP 3
74h 3 ECNT 1
78h 3 PCNT 2
7Ch 2 WCAP 6
80h 2 ECNT 2
84h 2 PCNT 3
88h 1 WCAP 10
8Ch 1 ECNT 3
90h 1 PCNT 4
The corresponding setup of the HTU control packet for this example is as follows:
IHADDR = 0x38 // points to WCAP data field
IFADDRA = 0x70 // points to buffer
ITCOUNT [frame count = 3] [element count = 3]
IHADDRCT = [DIR: Read HET and write to full address]
[SIZE: 32 bit]
[ADDMH: Increment HET address by 16 bytes]
[ADDMF: Post increment full address mode]
[Any transfer mode]
To Next Page
Loading...
Need help?
General
