Texas Instruments TMS570LC4357

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127
SPNU563A–March 2018
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Architecture
Table 2-2. Module Registers / Memories Memory-Map (continued)
Target Name
Memory
Select
Address Range
Frame Size Actual Size
Response for
Access to
Unimplemented
Locations in
FrameStart End
DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B Reads return
zeros, writes
have no effect
DCAN4 PS[7] 0xFFF7_E200 0xFFF7_E3FF 512B 512B Reads return
zeros, writes
have no effect
LIN1 PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B Reads return
zeros, writes
have no effect
SCI3 PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B Reads return
zeros, writes
have no effect
LIN2 PS[6] 0xFFF7_E600 0xFFF7_E6FF 256B 256B Reads return
zeros, writes
have no effect
SCI4 PS[6] 0xFFF7_E700 0xFFF7_E7FF 256B 256B Reads return
zeros, writes
have no effect
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B Reads return
zeros, writes
have no effect
MibSPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return
zeros, writes
have no effect
MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return
zeros, writes
have no effect
MibSPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B Reads return
zeros, writes
have no effect
MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B Reads return
zeros, writes
have no effect
System Modules Control Registers and Memories under PCR1 (Peripheral Segment 1)
DMA RAM PPCS[0] 0xFFF8_0000 0xFFF8_0FFF 4kB 4kB Abort
VIM RAM PPCS[2] 0xFFF8_2000 0xFFF8_2FFF 4kB 4kB Wrap around for
accesses to
unimplemented
address offsets
lower than
0x2FFF.
RTP RAM PPCS[3] 0xFFF8_3000 0xFFF8_3FFF 4kB 4kB Abort
Flash Wrapper PPCS[7] 0xFFF8_7000 0xFFF8_7FFF 4kB 4kB Abort
eFuse Farm
Controller
PPCS[12] 0xFFF8_C000 0xFFF8_CFFF 4kB 4kB Abort
Power Domain
Control (PMM)
PPSE[0] 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort
FMTM
Note: This module is
only used by TI during
test
PPSE[1] 0xFFFF_0400 0xFFFF_05FF 512B 512B Reads return
zeros, writes
have no effect
STC2 (NHET1/2) PPSE[2] 0xFFFF_0800 0xFFFF_08FF 256B 256B Reads return
zeros, writes
have no effect
SCM PPSE[2] 0xFFFF_0A00 0xFFFF_0AFF 256B 256B Abort