Texas Instruments TMS570LC4357

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SPNU563A–March 2018
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Architecture
Table 2-2. Module Registers / Memories Memory-Map (continued)
Target Name
Memory
Select
Address Range
Frame Size Actual Size
Response for
Access to
Unimplemented
Locations in
FrameStart End
EPC PPSE[3] 0xFFFF_0C00 0xFFFF_0FFF 1kB 1kB Abort
PCR1 registers PPSE[4]-
PPSE[5]
0xFFFF_1000 0xFFFF_17FF 2kB 2kB Reads return
zeros, writes
have no effect
NMPU (PS_SCR_S) PPSE[6] 0xFFFF_1800 0xFFFF_19FF 512B 512B Abort
NMPU (DMA Port A) PPSE[6] 0xFFFF_1A00 0xFFFF_1BFF 512B 512B Abort
Pin Mux Control
(IOMM)
PPSE[7] 0xFFFF_1C00 0xFFFF_1FFF 2kB 1kB Reads return
zeros, writes
have no effect
System Module -
Frame 2 (see platform
architecture
specification)
PPS[0] 0xFFFF_E100 0xFFFF_E1FF 256B 256B Reads return
zeros, writes
have no effect
PBIST PPS[1] 0xFFFF_E400 0xFFFF_E5FF 512B 512B Reads return
zeros, writes
have no effect
STC1 (Cortex-R5F) PPS[1] 0xFFFF_E600 0xFFFF_E6FF 256B 256B Reads return
zeros, writes
have no effect
DCC1 PPS[3] 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads return
zeros, writes
have no effect
DMA PPS[4] 0xFFFF_F000 0xFFFF_F3FF 1kB 1kB Abort
DCC2 PPS[5] 0xFFFF_F400 0xFFFF_F4FF 256B 256B Reads return
zeros, writes
have no effect
ESM register PPS[5] 0xFFFF_F500 0xFFFF_F5FF 256B 256B Reads return
zeros, writes
have no effect
CCM-R5 PPS[5] 0xFFFF_F600 0xFFFF_F6FF 256B 256B Reads return
zeros, writes
have no effect
DMM PPS[5] 0xFFFF_F700 0xFFFF_F7FF 256B 256B Reads return
zeros, writes
have no effect
L2RAMW PPS[6] 0xFFFF_F900 0xFFFF_F9FF 256B 256B Abort
RTP PPS[6] 0xFFFF_FA00 0xFFFF_FAFF 256B 256B Reads return
zeros, writes
have no effect
RTI + DWWD PPS[7] 0xFFFF_FC00 0xFFFF_FCFF 256B 256B Reads return
zeros, writes
have no effect
VIM PPS[7] 0xFFFF_FD00 0xFFFF_FEFF 512B 512B Reads return
zeros, writes
have no effect
System Module -
Frame 1 (see platform
architecture
specification)
PPS[7] 0xFFFF_FF00 0xFFFF_FFFF 256B 256B Reads return
zeros, writes
have no effect