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Memory Organization
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SPNU563A–March 2018
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Architecture
2.2.3.2 ECC Protection for Flash Accesses
The TMS570LC43x microcontrollers protect all accesses to the on-chip level 2 flash memory by dedicated
Single-Bit Error Correction Double-Bit Error Detection (SECDED) logic.
The access to the program memory – flash bank 0, 1 and 7 are protected by SECDED logic implemented
inside the ARM Cortex-R5F CPU.
The SECDED logic implementation uses Error Correction Codes (ECC) for correcting single-bit errors and
for detecting multiple-bit errors in the values read from the flash arrays. There is an 8-bit ECC for every 64
bits of data. The ECC for the level 2 flash memory contents needs to be calculated by an external tool
such as nowECC. The ECC can then be programmed into the flash array along with the actual application
code.
The ECC for the flash array is stored in the flash itself, and is mapped to a region starting at 0xF0400000
for the main flash bank 0 and 1, and to a region starting at 0xF0100000 for the EEPROM emulation flash
bank 7.
NOTE: The SECDED logic inside the CPU is permanently enabled for the AXI-M and AXI-S
interfaces.
Code Example for Enabling ECC Protection for Main Flash Accesses:
When the CPU detects an ECC single-, or double-bit error on a read from the flash memory, it signals this
on a dedicated “Event” bus. This event bus signaling is also not enabled by default and must be enabled
by the application. The below code example can be used to enable the CPU event signaling.
MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit ('X') of PMNC register
MRC p15,#0,r1,c9,c12,#0
The ECC error events exported onto the Event bus is first captured by the Error Profiling Controller (EPC)
module and in turn generates error signals that are input to the central Error Signaling Module (ESM).
2.2.3.3 Error Profiling Module (EPC)
The main idea of EPC is to enable the system to tolerate a certain amount of ECC correctable errors on
the same address repeatedly in the memory system with minimal runtime overhead. EPC will record
different single-bit error addresses in a Content Addressable Memory (CAM). If a correctable ECC error is
generated on a repeating address, the EPC will not raise an error to ESM module. This tolerance avoids
the application to handle the same error when the code is in a repeating loop. There are 4correctable error
interfaces implemented in EPC to capture correctable errors from 4 different sources. There are also 2
uncorrectable error interfaces implemented in EPC to capture uncorrectable errors from 2 different
sources. Main features of EPC are:
• Capture the addresses of the correctable ECC faults from different sources such as CPU cores, L2
SRAM and interconnect into a 32-entry CAM (Content Addressable Memory)
• For correctable faults, the error handling depends on the following conditions:
– if the incoming address is already in the 32-entry CAM, discard the fail. No error generated to ESM.
– if the address is not in the CAM list, and the CAM has empty entries, add the address into the CAM
list. In addition, raise the error signal to the ESM group 1 if enabled.
– if the address is not in the CAM list, and the CAM has no empty entries, always raise the error
signal to the ESM group 1.
• A 4-entry FIFO to store the correctable error events and addresses for each channel interface.
• For uncorrectable faults, capture the address and assert error signal to the ESM group 2.
Each EPC interface corresponds to a bit field in some of the EPC registers. Table 2-4 shows only those
registers that associate the bits to a specific interface for this device. See EPC chapter for the full list of
registers.
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