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FlexRay Module Registers
1311
SPNU563A–March 2018
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FlexRay Module
26.3.1.22 Clear on Event to System Memory Set/Reset (CESMS[1-4]/CESMR[1-4])
The Clear on Event to System Memory registers disables an enabled transfer on event (enabled in
ETESM) after a receive or transmit event. Four 32-bit registers reflect all possible 128 message buffers.
The bits are set by writing 1 to CESMSx and reset by writing 1 to CESMRx. Writing a 0 has no effect.
Reading from both addresses will result in the same value.
Figure 26-82. Clear on Event to System Memory Set 1 (CESMS1) [offset_TU = E0h]
31 16
CESMS1[31-16]
R/WS-0
15 0
CESMS1[15-0]
R/WS-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 26-62. Clear on Event to System Memory Set 1 (CESMS1) Field Descriptions
Bit Field Value Description
31-0 CESMS1[n] Clear on Event to System Memory Set 1. The register bits 0 to 31 correspond to message buffers 0
to 31. Each bit of the register enables an automatic clear of the corresponding ETESM1 bit after a
receive or transmit event:
0 No clear.
1 Activate clear.
Figure 26-83. Clear on Event to System Memory Reset 1 (CESMR1) [offset_TU = E4h]
31 16
CESMR1
R/WC-0
15 0
CESMR1
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-63. Clear on Event to System Memory Reset 1 (CESMR1) Field Descriptions
Bit Field Description
31-0 CESMR1 Clear on Event to System Memory Reset 1. The CESMR1 register shows the identical values to CESMS1 if
read.
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