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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.1.3 MibSPI /SPI Configurations
Table 28-2. MibSPI/SPI Configurations
MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MibSPI2 MIBSPI2SIMO[1:0], MIBSPI2SOMI[1:0], MIBSPI2CLK, MIBSPI2nCS[5:0], MIBSPI2nENA
MibSPI3 MIBSPI3SIMO[1:0], MIBSPI3SOMI[1:0], MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI4 MIBSPI4SIMO[1:0], MIBSPI4SOMI[1:0], MIBSPI4CLK, MIBSPI4nCS[5:0], MIBSPI4nENA
MibSPI5 MIBSPI5SIMO[1:0], MIBSPI5SOMI[1:0], MIBSPI51CLK, MIBSPI5nCS[5:0], MIBSP5nENA
SPI1 SPI1SIMO, ZSPI1SOMI, SPI1CLK, SPI2nCS[1:0], SPI1nENA
SPI2 SPI2SIMO, ZSPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI3 SPI3SIMO, ZSPI3SOMI, SPI3CLK, SPI3nCS[1:0], SPI3nENA
28.2 Basic Operation
This section details the basic operation principle of the SPI mode and the MibSPI mode operation of the
device.
28.2.1 SPI Mode
The SPI can be configured via software to operate as either a master or a slave. The MASTER bit
(SPIGCR1[0]) selects the configuration of the SPISIMO and SPISOMI pins. CLKMOD bit (SPIGCR1[1])
determines whether an internal or external clock source will be used.
The slave chip select (SPICS) pins are used when communicating with multiple slave devices or, with a
single slave, to delimit messages containing a leading register address. When a write occurs to SPIDAT1
in master mode, the SPICS pins are automatically driven to select the specified slave.
Handshaking mechanism, provided by the SPIENA pin, enables a slave SPI to delay the generation of the
clock signal supplied by the master if it is not prepared for the next exchange of data.
28.2.1.1 SPI Mode Operation Block Diagram
Figure 28-1 shows the SPI transaction hardware. TXBUF and RXBUF are internal buffers that are
intended to improve the overall throughput of data transfer. TXBUF is a transmit buffer, while RXBUF is a
receive buffer.
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