Control Registers
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-24. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions (continued)
Bit Field Value Description
15-0 TXDATA 0-FFFFh Transfer data. When written, these bits are copied to the shift register if it is empty. If the shift register
is not empty, then they are held in TXBUF.
SPIEN must be set to 1 before this register can be written to. Writing a 0 to SPIEN forces the lower
16 bits of SPIDAT1 to 0x0000.
A write to this register (or to the TXDATA field only) drives the contents of the CSNR field on the
SPICS pins, if the pins are configured as functional pins (automatic chip select, see Section 28.2.1).
When this register is read, the contents of TXBUF, which holds the latest data written, will be
returned.
Note: Regardless of the character length, the transmit data should be right-justified before
writing to the SPIDAT1 register.
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