Control Registers
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
NOTE: Reading from the INTVECT1 register when Transmit Empty is indicated does not clear the
TXINTFLG flag in the SPI Flag Register (SPIFLG). Writing a new word to the SPIDATx
register clears the Transmit Empty interrupt.
NOTE: In multi-buffer mode, INTVECT1 contains the interrupt for the highest priority transfer group.
A read from INTVECT1 automatically causes the next-highest priority transfer group's
interrupt status to get loaded into INTVECT1 and its corresponding SUSPEND flag to get
loaded into SUSPEND1. The transfer group with the lowest number has the highest priority,
and the transfer group with the highest number has the lowest priority.
Reading the INTVECT1 register when the RXOVRN interrupt is indicated in multi-buffer
mode does not clear the RXOVRN flag and hence does not clear the vector. The RXOVRN
interrupt vector may be cleared in multi-buffer mode either by write-clearing the RXOVRN
flag in the SPI Flag Register (SPIFLG) or by reading the RXRAM Overrun Buffer Address
Register (RXOVRN_BUF_ADDR).
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