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Control Registers
1573
SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-34. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions (continued)
Bit Field Value Description
25-24 PMODE3 Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4, or 8 data lines.
0 Normal operation/1-data line (MMODE3 should be set to 000).
1h 2-data line mode (MMODE3 should be set to 000).
2h 4-data line mode (MMODE3 should be set to 000).
3h 8-data line mode (MMODE3 should be set to 000).
23-22 Reserved 0 Reads return 0. Writes have no effect.
21 MODCLKPOL2 Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE2 bits are 000, this bit will be ignored.
0 Normal SPICLK in all the modes.
1 Polarity of the SPICLK will be inverted if Modulo mode is selected.
20-18 MMODE2 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0 1-data line mode (default). (PMODE2 should be set to 00).
1h 2-data line mode (PMODE2 should be set to 00).
2h 3-data line mode (PMODE2 should be set to 00).
3h 4-data line mode (PMODE2 should be set to 00).
4h 5-data line mode (PMODE2 should be set to 00).
5h 6-data line mode (PMODE2 should be set to 01).
6h-7h Reserved
17-16 PMODE2 Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4, or 8 data lines.
0 Normal operation/1-data line (MMODE2 should be set to 000).
1h 2-data line mode (MMODE2 should be set to 000).
2h 4-data line mode (MMODE2 should be set to 000).
3h 8-data line mode (MMODE2 should be set to 000).
15-12 Reserved 0 Reads return 0. Writes have no effect.
13 MODCLKPOL1 Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE1 bits are 000, this bit will be ignored.
0 Normal SPICLK in all the modes.
1 Polarity of the SPICLK will be inverted if Modulo mode is selected.
12-10 MMODE1 These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if
modulo option is supported by the module).
0 1-data line mode (default). (PMODE1 should be set to 00).
1h 2-data line mode (PMODE1 should be set to 00).
2h 3-data line mode (PMODE1 should be set to 00).
3h 4-data line mode (PMODE1 should be set to 00).
4h 5-data line mode (PMODE1 should be set to 00).
5h 6-data line mode (PMODE1 should be set to 01).
6h-7h Reserved
9-8 PMODE1 Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4, or 8 data lines.
0 Normal operation/1-data line (MMODE1 should be set to 000).
1h 2-data line mode (MMODE1 should be set to 000).
2h 4-data line mode (MMODE1 should be set to 000).
3h 8-data line mode (MMODE1 should be set to 000).
7-6 Reserved 0 Reads return 0. Writes have no effect.
5 MODCLKPOL0 Modulo mode SPICLK polarity. This bit determines the polarity of the SPICLK in modulo
mode only. If the MMODE0 bits are 000, this bit will be ignored.
0 Normal SPICLK in all the modes.
1 Polarity of the SPICLK will be inverted if Modulo mode is selected.
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