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Control Registers
1589
SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.3.37 DMA Large Count (DMACNTLEN)
Figure 28-73. DMA Large Count Register (DMACNTLEN) [offset = 118h]
31 16
Reserved
R-0
15 1 0
Reserved LARGE COUNT
R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 28-46. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 LARGE COUNT Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL.
0 Select the DMAxCTRL counters. Writes to the DMAxCTRL register will modify the ICOUNT
value. Reading ICOUNT and COUNT can be done from the DMAxCTRL register. The
DMAxCOUNT register should not be used since any write to this register will be overwritten by
a subsequent write to the DMAxCTRL register to set the TXDMAENA or RXDMAENA bits.
1 Select the DMAxCOUNT counters. Writes to the DMAxCTRL register will not modify the
ICOUNT value. The ICOUNT value must be written to in the DMAxCOUNT register before the
RXDMAENA or TXDMAENA bits are set in the DMAxCTRL register. The DMAxCOUNT register
should be used for reading COUNT or ICOUNT.
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