Texas Instruments TMS570LC4357

Parity\ECC Memory www.ti.com
1612
SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.5 Parity\ECC Memory
Parity/ECC portion of multi-buffer RAM is not accessible by the CPU during normal operating modes.
However each read or write operation to the Control/Data/Status portion of the multi-buffer RAM causes
reads/writes to the parity/ECC portion as well.
• Each write to the multi-buffer RAM (either from the VBUS interface or by the MibSPI itself) causes a
write operation to the Parity/ECC portion of RAM simultaneously to update the equivalent parity/ECC
bits.
• Each read operation from the multi-buffer RAM (either from the VBUS interface or by the MibSPI itself)
causes a read operation from the Parity/ECC portion of the RAM for parity/ECC comparison purpose.
• Reads/Writes to multi-buffer RAM could either be caused by any CPU/DMA accesses or by the
Sequencer logic of MibSPI itself.
For testing the Parity/ECC portion of the multi-buffer RAM that is a 4-bit or 7-bit field per word address, a
separate parity/ECC memory test mode is available. The parity memory test mode can be enabled and
disabled by the PTESTEN bit in PAR_ECC_CTRL register and the ECCDIAG_EN bit in ECCDIAG_CTRL
register.
During the parity test mode, the parity locations are addressable at the address between
RAM_BASE_ADDR + 0x400h and RAM_BASE_ADDR + 0x7FFh. Each location corresponds,
sequentially, to each TXRAM word, then to each RXRAM word. See Figure 28-90 for a diagram of the
memory map of parity memory during normal operating mode and during parity test mode while
EXTENDED_BUF mode is disabled or the feature is not implemented. See Figure 28-91 for a diagram of
the memory map of parity memory during normal operating mode and during parity test mode while
EXTENDED_BUF mode is enabled.
During Parity/ECC test mode, after writing the Data/Control portion of the RAM, the Parity/ECC locations
can be written with wrong parity/ECC bits to intentionally cause Parity/ECC Errors.
See the device-specific data sheet to get the actual base address of the multi-buffer RAM.
NOTE: The RX_RAM_ACCESS bit can also be set to 1 during the Parity/ECC Test mode to be able
to write to RXRAM locations for test purpose. Both Parity/ECC bits testing and RXRAM
testing can be done together.
There are 4 bits of parity corresponding to each of the 32-bit multi-buffer locations. Individual bits in the
parity memory are byte-addressable in parity test mode. See the example in Section 28.5.1 for further
details.
If ECC is enabled, there are 7 ECC-bits corresponding to each of the 32-bit multi-buffer locations. See the
example in Section 28.5.1 for further details.
NOTE: Polarity of the parity (odd/even) varies by device. In some devices, a control register in the
system module can be used to select odd or even parity.