MibSPI Pin Timing Parameters
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.6.3 Master Mode Timing Parameter Details
In case of Master, the module drives out SPICLK. It also drives out the Transmit data on SPISIMO with
respect to its internal SPICLK. In case of Master mode, the RX data on the SPISOMI pin is registered with
respect to SPICLK received through the input buffer from the I/O pad.
If the chip select pin is functional, then the Master will drive out the SPICS pins before starting the
SPICLK. If the SPIENA pin is functional, then the Master will wait for an active low from the Slave on the
input pin to start the SPICLK.
28.6.4 Slave Mode Timing Parameter Details
In case of Slave mode, the module will drive only the SPISOMI and SPIENA pins. All other pins are inputs
to it. The RX data on the SPISIMO pin will be registered with respect to the SPICLK pin. The Slave will
use the SPICS pin to drive out the SPIENA pin if both are functional. If 4-pin with SPIENA is configured,
then the Slave will drive out an active-low signal on the SPIENA pin when new data is written to the TX
Shift Register. Irrespective of 4-pin with SPIENA or 5-pin configuration, the Slave will deassert the
SPIENA pin after the last bit is received. If ENABLE_HIGHZ (SPIINT0.24) bit is 0, the de-asserted value of
the SPIENA pin will be 1. Otherwise, it will depend upon the internal pull up or pull down resistor (if
implemented) depending upon the Specification of the Chip.
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