Addr Data
Addr
Start
Start
Address frame
(address bit = 1)
Data frame
(address bit = 0)
Idle time
is of no
significance
One block
Several blocks of frames
Data format
(pins LINRX,
LINTX)
Data format
expanded
Start
1
0 1
Idle time is not significant
Parity
Stop
Parity
Stop
Parity
Stop
Idle time
is of no
significance
Address frame
(address bit = 1)
Address
Data
Last data
Start
Start
Start
Address frame
Data frame
Fewer than
10 idle bits
Idle period
One block of frames
Blocks separated by 10 or more idle bits
Blocks of frames
Data format
(pins LINRX,
LINTX)
Data format
expanded
Stop
Stop
Stop
Data frame
Parity
Parity
Parity
SCI
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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
Figure 29-6. Idle-Line Multiprocessor Communication Format
29.2.1.4.2 Address-Bit Multiprocessor Mode
In the address-bit protocol, each frame has an extra bit immediately following the data field called an
address bit. A frame with the address bit set to 1 is an address frame; a frame with the address bit set to 0
is a data frame. The idle period timing is irrelevant in this mode. Figure 29-7 illustrates the format of
several blocks and frames with the address-bit mode.
When address-bit mode is used, the value of the TXWAKE bit is the value sent as the address bit. To
send an address frame, software must set the TXWAKE bit. This bit is cleared as the contents of the
SCITD are shifted from the TXWAKE register so that all frames sent are data except when the TXWAKE
bit is written as a 1.
No dummy write to SCITD is required before an address frame is sent in address-bit mode. The first byte
written to SCITD after the TXWAKE bit is written to 1 is transmitted with the address bit set when address-
bit mode is used.
Figure 29-7. Address-Bit Multiprocessor Communication Format
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