V C L K
a
Td
M
Pb itT
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1 6
11 6
VCLK
i
Td
M
PbitT
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16
116
LIN
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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.3.1.4.2 Superfractional Divider
The superfractional divider scheme applies to the following modes:
• LIN master mode (synch field + identifier field + response field + checksum field)
• LIN slave mode (response field + checksum field)
29.3.1.4.3 Superfractional Divider In LIN Mode
Building on the 4-bit fractional divider M (BRS[27:24], the superfractional divider uses an additional 3-bit
modulating value, illustrated in Table 29-7. The sync field (0x55), the identifier field and the response field
can all be seen as 8-bit data bytes flanked by a start bit and a stop bit. The bits with a 1 in the table will
have an additional VCLK period added to their T
bit
.
(1)
1. In LIN master mode bit modulation applies to synch field + identifier field + response field
2. In LIN slave mode bit modulation applies to identifier field + response field
Table 29-7. Superfractional Bit Modulation for LIN Master Mode and Slave Mode
(1)
BRS[30:28] Start Bit D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] Stop Bit
0h 0 0 0 0 0 0 0 0 0 0
1h 1 0 0 0 0 0 0 0 1 0
2h 1 0 0 0 1 0 0 0 1 0
3h 1 0 1 0 1 0 0 0 1 0
4h 1 0 1 0 1 0 1 0 1 0
5h 1 1 1 0 1 0 1 0 1 1
6h 1 1 1 0 1 1 1 0 1 1
7h 1 1 1 1 1 1 1 0 1 1
The baud rate will vary over a LIN data field to average according to the BRS[30:28] value by a d fraction
of the peripheral internal clock: 0<d<1.
The instantaneous bit time is expressed in terms of T
VCLK
as follows:
For all P other than 0, and all M and d (0 or 1),
(47)
For P = 0 T
bit
= 32T
VCLK
The averaged bit time is expressed in terms of T
VCLK
as follows:
For all P other than 0, and all M and d (0<d<1),
(48)
For P = 0 T
bit
= 32T
VCLK
With the superfractional divider, a LIN baud rate of 20 kbps is achievable with an internal clock VCLK of
726 kHz. Furthermore, a rate of 400 kbps is achievable with an VCLK of 14.6 MHz.
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