LIN
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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.3.4 LIN Configurations
The following list details the configuration steps that software should perform prior to the transmission or
reception of data in LIN mode. As long as the SWnRST bit in the SCIGCR1 register is cleared to 0 the
entire time that the LIN is being configured, the order in which the registers are programmed is not
important.
• Enable LIN by setting the RESET bit in SCIGCR0 to 1.
• Clear the SWnRST bit to 0 before LIN is configured.
• Select the desired frame format by programming the SCIGCR1 register.
• Set both the RX FUNC and TX FUNC bits in SCIPIO0 to 1 to configure the LINRX and LINTX pins for
LIN functionality.
• Set the LIN MODE bit in SCIGCR1 to 1 to enable LIN mode.
• Select Master or Slave mode by programming the CLOCK bit in SCIGCR1.
• Set the MBUF MODE bit in SCIGCR1 to 1 to select multi-buffer mode.
• Select the baud rate to be used for communication by programming the BRS register.
• Set the maximum baud rate to be used for communication by programming the BMRS register.
• Set the CONT bit in SCIGCR1 to 1 to make LIN not halt for an emulation breakpoint until its current
reception or transmission is complete (this bit is used only in an emulation environment).
• Set the LOOP BACK bit in SCIGCR1 to 1 to connect the transmitter to the receiver internally (this
feature is used to perform a self-test).
• Set the RXENA bit in SCIGCR1 to 1, if data is to be received.
• Set the TXENA bit in SCIGCR1 to 1, if data is to be transmitted.
• Select the RX ID MASK and the TX ID MASK fields in the LINMASK register.
• Set the SWnRST bit to 1 after LIN is configured.
• Perform receiving or transmitting data (see Section 29.3.4.1 or Section 29.3.4.2).
29.3.4.1 Receiving Data
The LIN receiver is enabled to receive messages if both the RX FUNC bit and the RXENA bit are set to 1.
If the RX FUNC bit is not set, the LINRX pin functions as a general-purpose I/O pin rather than as a LIN
function pin.
The ID RX FLAG is set after a valid LIN ID is received with RX Match. An ID interrupt is generated, if
enabled.
29.3.4.1.1 Receiving Data in Single-Buffer Mode
Single-buffer mode is selected when the MBUF MODE bit is cleared to 0. In this mode, LIN sets the
RXRDY bit when it transfers newly received data from SCIRXSHF to RD0. The SCI clears the RXRDY bit
after the new data in RD0 has been read. Also, as data is transferred from SCIRXSHF to RD0, the LIN
sets the FE, OE, or PE flags if any of these error conditions were detected in the received data. These
error conditions are supported with configurable interrupt capability.
You can receive data by:
1. Polling Receive Ready Flag
2. Receive Interrupt
3. DMA
In polling method, software can poll for the RXRDY bit and read the data from RD0 byte of the LINRD0
register once the RXRDY bit is set high. The CPU is unnecessarily overloaded by selecting the polling
method. To avoid this, you can use either the interrupt or DMA method. To use the interrupt method, the
SET RX INT bit is set. To use the DMA method, the SET RX DMA bit is set. Either an interrupt or a DMA
request is generated the moment the RXRDY bit is set. If the checksum scheme is enabled by setting the
Compare Checksum (CC) bit to 1, the checksum will be compared on the byte that is currently being
received, which is expected to be the checksum byte. The CC bit will be cleared once the checksum is
received. A CE will immediately be flagged if there is a checksum error.
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