Texas Instruments TMS570LC4357 - Page 1679

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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
Table 29-17. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions (continued)
Bit Field Value Description
27 CLR NRE INT Clear no-response-error interrupt. This bit is effective in LIN mode only. This bit disables the
NRE interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
26 CLR FE INT Clear framing-error interrupt. This bit is effective in LIN or SCI mode. This bit disables the
framing-error interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
25 CLR OE INT Clear overrun-error interrupt. This bit is effective in LIN or SCI mode. This bit disables the
SCI/LIN overrun error interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
24 CLR PE INT Clear parity interrupt. This bit is effective in LIN or SCI mode. This bit disables the parity error
interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
23-19 Reserved 0 Reads return 0. Writes have no effect.
18 CLR RX DMA ALL Clear receive DMA all. This bit is effective in SCI mode only. This bit clears the receive DMA
request for address frames when set. Only receive data frames generate a DMA request.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The receive DMA request for address and data frames is enabled.
Write: The receive DMA request for address and data frames is disabled.
17 CLR RX DMA Clear receive DMA request. This bit is effective in LIN or SCI mode. This bit disables the
receive DMA request when set.
0 Read: The receive DMA request is disabled.
Write: No effect.
1 Read: The receive DMA request is enabled.
Write: The receive DMA request for is disabled.
16 CLR TX DMA Clear transmit DMA request. This bit is effective in LIN or SCI mode. This bit disables the
transmit DMA request when set.
0 Read: The transmit DMA request is disabled.
Write: No effect.
1 Read: The transmit DMA request is enabled.
Write: The transmit DMA request for is disabled.
15-14 Reserved 0 Reads return 0. Writes have no effect.
13 CLR ID INT Clear ID interrupt. This bit is effective in LIN mode only. This bit disables the ID interrupt when
set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.