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SCI/LIN Control Registers
1689
SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
Table 29-20. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit Field Value Description
26 FE Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an
expected stop bit is not found. In SCI compatibility mode, only the first stop bit is checked. The
missing stop bit indicates that synchronization with the start bit has been lost and that the character
is incorrectly framed. Detection of a framing error causes the SCI/LIN to generate an error interrupt
if the SET FE INT bit is set in the register SCISETINT. The framing error flag is cleared by the
following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reading the corresponding interrupt offset in SCIINTVECT0/1
• Reception of a new character/frame, depending on whether the module is in SCI compatible or
LIN mode
In multi-buffer mode the frame is defined in the SCIFORMAT register.
0 Read: No framing error has been detected since the last clear.
Write: No effect.
1 Read: A framing error has been detected since the last clear.
Write: The bit is cleared to 0.
25 OE Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when the
transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy
buffers in LINRD0 and LINRD1. Detection of an overrun error causes the LIN to generate an error
interrupt if the SET OE INT bit = 1. The OE flag is reset by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reading the corresponding interrupt offset in SCIINTVECT0/1
0 Read: No overrun error has been detected since the last clear.
Write: No effect.
1 Read: An overrun error has been detected.
Write: The bit is cleared to 0.
24 PE Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity
error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data
and address bit fields of the received frame. In idle-line mode, only the data is used to calculate
parity. An error is generated when a character is received with a mismatch between the number of
1s and its parity bit. If the parity function is disabled (SCIGCR[2] = 0), the PE flag is disabled and
read as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE
INT bit = 1. The PE bit is reset by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reception of a new character or frame, depending on whether the module is in SCI compatible
or LIN mode, respectively.
• Reading the corresponding interrupt offset in SCIINTVECT0/1
0 Read: No parity error has been detected since the last clear.
Write: No effect.
1 Read: A parity error has been detected.
Write: The bit is cleared to 0.
23-15 Reserved 0 Reads return 0. Writes have no effect.
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