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SCI/LIN Control Registers
1693
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
Table 29-20. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit Field Value Description
2 IDLE SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the
SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not
receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The
SCI enters the idle state if one of the following events occurs:
• A system reset
• An SCI software reset
• A power down
• The RX pin is configured as a general I/O pin
0 The idle period has been detected; the SCI is ready to receive.
1 The idle period has not been detected; the SCI will not receive any data.
1 WAKEUP Wakeup flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or
transmitter activity has taken the module out of power-down mode. An interrupt is generated if the
SET WAKEUP INT bit (SCISETINT[2]) is set. It is cleared by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reading the corresponding interrupt offset in SCIINTVECT0/1
For compatibility mode, see the SCI document for more information on low-power mode.
0 Read: The module will not wake up from power-down mode.
Write: No effect.
1 Read: Wake up from power-down mode.
Write: The bit is cleared to 0.
0 BRKDT SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI
detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains
continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error.
Detection of a break condition causes the SCI to generate an error interrupt if the SET BRKDT INT
bit is set. The BRKDT bit is reset by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reading the corresponding interrupt offset in SCIINTVECT0/1
0 Read: No break condition has been detected since the last clear.
Write: No effect.
1 Read: A break condition has been detected.
Write: The bit is cleared to 0.
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