Isosynchronous baud value =
)(
VCLK Frequency
2
Asynchronous baud value =
)(
VCLK Frequency
32
Isosynchronous baud value =
)(
VCLK Frequency
P + 1
Asynchronous baud value =
( )
VCLK Frequency
16
P + 1 +
M
16
)(
SCI/LIN Control Registers
www.ti.com
1696
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.7.12 Baud Rate Selection Register (BRS)
This section describes the baud rate selection register. Figure 29-39 and Table 29-24 illustrate this
register.
Figure 29-39. Baud Rate Selection Register (BRS) (offset = 2Ch)
31 30 28 27 24 23 16
Rsvd U M PRESCALER P
R-0 R/W-0 R/W-0 R/W-0
15 0
PRESCALER P
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29-24. Baud Rate Selection Register (BRS) Field Descriptions
Bit Field Value Description
31 Reserved 0 Reads return 0. Writes have no effect.
30-28 U 0-2h SCI/LIN super fractional divider selection. These bits are effective in LIN or SCI asynchronous
mode. These bits are an additional fractional part for the baud rate specification. These bits
allow a super-fine tuning of the fractional baud rate with seven more intermediate values for
each of the M fractional divider values. See Section 29.3.1.4.1 for more details.
27-24 M 0-3h SCI/LIN 4-bit fractional divider selection. These bits are effective in LIN or SCI asynchronous
mode. These bits are used to select a baud rate for the SCI/LIN module, and they are a
fractional part for the baud rate specification. The M divider allows fine-tuning of the baud rate
over the P prescaler with 15 additional intermediate values for each of the P integer values. See
Section 29.3.1.4.1 for more details.
23-0 PRESCALER P 0-FF FFFFh These bits are used to select a baud rate for the SCI/LIN module. These bits are effective in
LIN mode and SCI compatibility.
The SCI/LIN has an internally generated serial clock determined by the VCLK and the
prescalers P and M in this register. The LIN uses the 24-bit integer prescaler P value of this
register to select one of over 16,700,000. The additional 4-bit fractional divider M refines the
baud rate selection PRESCALER[27:24].
NOTE: In LIN mode, ONLY the asynchronous mode and baud rate values are used.
The baud rate can be calculated using the following formulas:
(52)
(53)
For P = 0,
(54)
(55)
Table 29-25 contains comparative baud values for different P values, with VCLK = 50 MHz, for
asynchronous mode.