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SCI Control Registers
1737
SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
Table 30-5. SCI Global Control Register 1 (SCIGCR1) Field Descriptions (continued)
Bit Field Value Description
3 PARITY SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity.
0 Odd parity is used.
1 Even parity is used.
The parity bit is calculated based on the data bits in each frame and the address bit (in
address-bit mode). The start and stop fields in the frame are not included in the parity
calculation.
For odd parity, the SCI transmits and expects to receive a value in the parity bit that makes
odd the total number of bits in the frame with the value of 1.
For even parity, the SCI transmits and expects to receive a value in the parity bit that makes
even the total number of bits in the frame with the value of 1.
2 PARITY ENA Parity enable. This bit enables or disables the parity function.
0 Parity is disabled; no parity bit is generated during transmission or is expected during reception.
1 Parity is enabled. A parity bit is generated during transmission and is expected during reception.
1 TIMING MODE SCI timing mode bit.
0 Synchronous timing is used.
1 Asynchronous timing is used.
0 COMM MODE SCI communication mode bit.
0 Idle-line mode is used.
1 Address-bit mode is used.
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