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SCI Control Registers
1739
SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
Table 30-6. SCI Set Interrupt Register (SCISETINT) Field Descriptions (continued)
Bit Field Value Description
16 SET TX DMA Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. If it is
cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT).
0 Read: Transmit DMA request is disabled.
Write: No effect.
1 Read or write: Transmit DMA request is enabled.
15-10 Reserved 0 Reads return 0. Writes have no effect.
9 SET RX INT Receiver interrupt enable. Setting this bit enables the SCI to generate a receive interrupt after a
frame has been completely received and the data is being transferred from SCIRXSHF to
SCIRD.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
8 SET TX INT Set transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data
is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
7-2 Reserved 0 Reads return 0. Writes have no effect.
1 SET WAKEUP INT Set wakeup interrupt. Setting this bit enables the SCI to generate a wakeup interrupt and
thereby exit low-power mode. If enabled, the wakeup interrupt is asserted when local low-power
mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin
during low-power mode.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
0 SET BRKDT INT Set breakdetect interrupt. Setting this bit enables the SCI to generate an error interrupt if a
break condition is detected on the SCIRX pin.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read or write: The interrupt is enabled.
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