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SCI Control Registers
1741
SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
Table 30-7. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions (continued)
Bit Field Value Description
17 CLR RX DMA Clear receive DMA request. This bit disables the receive DMA request when set.
0 Read: The DMA request is disabled.
Write: No effect.
1 Read: The receive DMA request is enabled.
Write: The receive DMA request for is disabled.
16 CLR TX DMA Clear transmit DMA request. This bit disables the transmit DMA request when set.
0 Read: Transmit DMA request is disabled.
Write: No effect.
1 Read: The transmit DMA request is enabled.
Write: The transmit DMA request for is disabled.
15-10 Reserved 0 Reads return 0. Writes have no effect.
9 CLR RX INT Clear receiver interrupt. This bit disables the receiver interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
8 CLR TX INT Clear transmitter interrupt. This bit disables the transmitter interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
7-2 Reserved 0 Reads return 0. Writes have no effect.
1 CLR WAKEUP INT Clear wakeup interrupt. This bit disables the wakeup interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
0 CLR BRKDT INT Clear breakdetect interrupt. This bit disables the break-detect interrupt when set.
0 Read: The interrupt is disabled.
Write: No effect.
1 Read: The interrupt is enabled.
Write: The interrupt is disabled.
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