SCI Control Registers
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SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
30.7.5 SCI Set Interrupt Level Register (SCISETINTLVL)
Figure 30-12 and Table 30-8 illustrate this register. This register is used to set the interrupt level for the
supported interrupts.
Figure 30-12. SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h]
31 27 26 25 24
Reserved SET FE
INT LVL
SET OE
INT LVL
SET PE
INT LVL
R-0 R/W-0 R/W-0 R/W-0
23 19 18 17 16
Reserved
SET RX DMA
ALL INT LVL
Reserved
R-0 R/W-0 R-0
15 10 9 8
Reserved SET RX
INT LVL
SET TX
INT LVL
R-0 R/W-0 R/W-0
7 2 1 0
Reserved
SET WAKEUP
INT LVL
SET BRKDT
INT LVL
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30-8. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions
Bit Field Value Description
31-27 Reserved 0 Reads return 0. Writes have no effect.
26 SET FE INT LVL Set framing-error interrupt level.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
25 SET CE INT LVL Set overrun-error interrupt level.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
24 SET PE INT LVL Set parity error interrupt level.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
23-19 Reserved 0 Reads return 0. Writes have no effect.
18 SET RX DMA ALL LVL Set receive DMA all interrupt levels.
0 Read: The receive interrupt request for address frames is mapped to the INT0 line.
Write: No effect.
1 Read or write: The receive interrupt request for address frames is mapped to the INT1 line.
17-10 Reserved 0 Reads return 0. Writes have no effect.
9 SET RX INT LVL Set receiver interrupt level.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.