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SCI Control Registers
1743
SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
Table 30-8. SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions (continued)
Bit Field Value Description
8 SET TX INT LVL Set transmitter interrupt level.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
7-2 Reserved 0 Reads return 0. Writes have no effect.
1 SET WAKEUP INT LVL Set wakeup interrupt level.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
0 SET BRKDT INT LVL Set breakdetect interrupt level.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read or write: The interrupt level is mapped to the INT1 line.
30.7.6 SCI Clear Interrupt Level Register (SCICLEARINTLVL)
Figure 30-13 and Table 30-9 illustrate this register.
Figure 30-13. SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h]
31 27 26 25 24
Reserved CLR FE
INT LVL
CLR OE
INT LVL
CLR PE
INT LVL
R-0 R/W-0 R/W-0 R/W-0
23 19 18 17 16
Reserved
CLR RX DMA
ALL INT LVL
Reserved
R-0 R/W-0 R-0
15 10 9 8
Reserved CLR RX
INT LVL
CLR TX
INT LVL
R-0 R/W-0 R/W-0
7 2 1 0
Reserved
CLR WAKEUP
INT LVL
CLR BRKDT
INT LVL
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30-9. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions
Bit Field Value Description
31-27 Reserved 0 Reads return 0. Writes have no effect.
26 CLR FE INT LVL Clear framing-error interrupt.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
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