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SCI Control Registers
1747
SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
Table 30-10. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit Field Value Description
9 RXRDY Receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is
ready to be read by the CPU or DMA. The SCI generates a receive interrupt when RXRDY flag bit
is set if the SET RX INT bit (SCISETINT[9]) is set. RXRDY is cleared by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reading the SCIRD register in compatibility mode
• Reading the last data byte RDy of the response in LIN mode
Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
0 Read: No new data is in SCIRD.
Write: No effect.
1 Read: New data is ready to be read from SCIRD.
Write: The bit is cleared to 0.
8 TXRDY Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer is ready to
get another character from a CPU or DMA write.
Writing data to SCITD automatically clears this bit. This bit is set after the data of the TX buffer is
shifted into the SCITXSHF register. This event can trigger a transmit interrupt after data is copied to
the TX shift register SCITXSHF, if the interrupt enable bit TXINT is set.
Note: 1) TXRDY is also set to 1 by setting of the RESET bit, enabling SWnRST, or by a
system reset.
2) The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the
SCIINTVECT0/1 register.
3) The transmit interrupt request can be eliminated until the next series of data written into
the transmit buffers LINTD0 and LINTD1, by disabling the corresponding interrupt via the
SCICLEARINT register or by disabling the transmitter via the TXENA bit (SCIGCR1[25]).
0 SCITD is full.
1 SCITD is ready to receive the next character.
7-4 Reserved 0 Reads return 0. Writes have no effect.
3 BUSY Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. As
soon as the receiver detects the beginning of a start bit, the BUSY bit is set to 1. When the
reception of a frame is complete, the SCI clears the BUSY bit. If SET WAKEUP INT bit
(SCISETINT[2]) is set and power down is requested while this bit is set, the SCI automatically
prevents low-power mode from being entered and generates wakeup interrupt. The BUSY bit is
controlled directly by the SCI receiver, but this bit can also be cleared by the following:
• Setting the SWnRST bit
• Setting of the RESET bit
• A system reset occurring
0 The receiver is not currently receiving a frame.
1 The receiver is currently receiving a frame.
2 IDLE SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself
with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle
for 11 bit periods to clear this bit. The SCI enters the idle state if one of the following events occurs:
• A system reset
• An SCI software reset
• A power down
• The RX pin is configured as a general I/O pin
0 The idle period has been detected; the SCI is ready to receive.
1 The idle period has not been detected; the SCI will not receive any data.
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