SCI Control Registers
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SPNU563A–March 2018
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Serial Communication Interface (SCI) Module
Table 30-10. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit Field Value Description
24 PE Parity error flag. This bit is set when a parity error is detected in the received data. In SCI address-
bit mode, the parity is calculated on the data and address bit fields of the received frame. In idle-
line mode, only the data is used to calculate parity. An error is generated when a character is
received with a mismatch between the number of 1s and its parity bit. If the parity function is
disabled (SCIGCR[2] = 0), the PE flag is disabled and read as 0. Detection of a parity error causes
the LIN to generate an error interrupt if the SET PE INT bit (SCISETINT[24]) is set. The PE bit is
reset by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reception of a new character or frame, depending on whether the module is in SCI compatible
or LIN mode, respectively
• Reading the corresponding interrupt offset in SCIINTVECT0/1
0 Read: No parity error has been detected since the last clear.
Write: No effect.
1 Read: A parity error has been detected since the last clear.
Write: The bit is cleared to 0.
23-13 Reserved 0 Reads return 0. Writes have no effect.
12 RXWAKE Receiver wakeup detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an
address. RXWAKE is cleared by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Upon receipt of a data frame
0 The data in SCIRD is not an address.
1 The data in SCIRD is an address.
11 TX EMPTY Transmitter empty flag. This flag indicates the transmitter's buffer register(s) (SCITD/TDy) and shift
register (SCITXSHF) are empty.
Note: The RESET bit, an active SWnRST (SCIGCR1[7]), or a system reset sets this bit. This
bit does not cause an interrupt request.
0 Transmitter buffer or shift register (or both) are loaded with data.
1 Transmitter buffer and shift registers are both empty.
10 TXWAKE Transmitter wakeup method select. The TXWAKE bit controls whether the data in SCITD should be
sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or
0 by software before a byte is written to SCITD and is cleared by the SCI when data is transferred
from SCITD to SCITXSHF or by a system reset.
Note: TXWAKE is not cleared by the SWnRST bit.
Address-bit mode
0 Frame to be transmitted will be data (address bit = 0).
1 Frame to be transmitted will be an address (address bit = 1).
Idle-line mode
0 The frame to be transmitted will be data.
1 The following frame to be transmitted will be an address (writing a 1 to this bit followed by writing
dummy data to the SCITD will result in a idle period of 11 bit periods before the next frame is
transmitted).
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