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Overview
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SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
31.1.2 Functional Overview
The I2C module is a serial bus that supports multiple master devices. In multimaster mode, one or more
devices can be connected to the same bus and are capable of controlling the bus. Each I2C device on the
bus is recognized by a unique address and can operate as either a transmitter or a receiver, depending on
the function of the device. In addition to being a transmitter or receiver, a device connected to the I2C bus
can also be considered a master or a slave when performing data transfers.
NOTE: A master device is the device that initiates the data transfer on a bus and generates the
clock signal that permits the transfer. During the transmission, any device addressed by the
master is considered the slave.
Data is communicated to devices interfacing to the I2C module using the serial data pin (SDA) and the
serial clock pin (SCL) as shown in Figure 31-2. These two wires carry information between the device and
the other devices connected to the I2C bus. Both SDA and SCL pins on the device are bidirectional. They
must be connected to a positive supply voltage through a pull-up resistor. When the bus is free, both pins
are high. The driver of these two pins has an open-drain configuration to perform the wired-AND function.
The device has a special mode that can be entered to ignore a NACK generated from non-compliant I2C
devices that are incapable of generating an ACK.
The I2C module consists of the following primary blocks:
• A serial Interface: one data pin (SDA) and one clock pin (SCL)
• The device register interface
– Data registers to temporarily hold received data and transmitted data traveling between the SDA
pin and the CPU or the DMA
– Control and status registers
• A prescaler to divide down the input clock that is driven to the I2C module
• A peripheral bus interface to enable the CPU and DMA to access the I2C module registers
• An arbitrator to handle arbitration between the I2C module (when configured as a master) and another
master
• Interrupt generation logic (interrupts can be sent to the CPU)
• A clock synchronizer that synchronizes the I2C input clock (from the system module) and the clock on
the SCL pin, and synchronizes data transfers with masters of different clock speeds.
• A noise filter on each of the two serial pins
• DMA event generation logic that synchronizes data reception and data transmission in the I2C module
for DMA transmission
In Figure 31-2, the CPU or the DMA writes data for transmission to I2CDXR and reads received data
from I2CDRR. When the I2C module is configured as a transmitter, data written to I2CDXR is copied to
I2CXSR and shifted out one bit at a time. When the I2C module is configured as a receiver, received
data is shifted into I2CRSR and then copied to I2CDRR.
When the I2C function is not needed, the pins may be controlled as general-purpose input/output
(GPIO) pins. The I/O structure of each pin includes:
• programmable slew rate control of the outputs
• open drain mode
• programmable pull enable/disable on the input
• programmable pull up/pull down function on the input
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