1
2
3
. .
n
SCL
SDA
Master
Slaves
Overview
www.ti.com
1766
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Inter-Integrated Circuit (I2C) Module
31.1 Overview
The I2C has the following features:
• Compliance to the Philips I
2
C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
– Bit/Byte format transfer
– 7-bit and 10-bit device addressing modes
– General call
– START byte
– Multi-master transmitter/ slave receiver mode
– Multi-master receiver/ slave transmitter mode
– Combined master transmit/receive and receive/transmit mode
– Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
• Free data format
• Two DMA events (transmit and receive)
• DMA event enable/disable capability
• Seven interrupts that can be used by the CPU
• Operates with VBUS frequency from 6.7 MHz up
• Operates with module frequency between 6.7 MHz to 13.3 MHz
• Module enable/disable capability
• The SDA and SCL are optionally configurable as general purpose I/O
• Slew rate control of the outputs
• Open drain control of the outputs
• Programmable pullup/pulldown capability on the inputs
• Supports Ignore NACK mode
NOTE: This I2C module does not support:
• High-speed (HS) mode
• C-bus compatibility mode
• The combined format in 10-bit address mode (the I2C sends the slave address second
byte every time it sends the slave address first byte)
31.1.1 Introduction to the I2C Module
The I2C module supports any slave or master I2C-compatible device. Figure 31-1 shows an example of
multiple I2C serial ports connected for a two-way transfer from one device to another device.
Figure 31-1. Multiple I2C Modules Connection Diagram
To Next Page
Loading...
Need help?
General
