Data line
SDA
SCL
stable data
Change of
data allowed
I2C Module Operation
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SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
NOTE: The master clock frequency defined above does not include rise/fall time and latency of the
synchronizer inside the module. The actual transfer rate will be slower than the value
calculated from the formula above. Also, due to the nature of SCL synchronization, the SCL
clock period could change if SCL synchronization is taking place.
31.2 I2C Module Operation
The following section discusses how the I2C module operates.
31.2.1 Input and Output Voltage Levels
One clock pulse is generated by the master device for each data bit transferred. Because of a variety of
different technology devices that can be connected to the I2C-bus, the levels of logic 0 (low) and logic 1
(high) are not fixed and depend on the associated level of V
CCIO
. For details, see the device specific data
sheet.
31.2.2 I2C Module Reset Conditions
The I2C module can be reset in the following two ways:
• Through the global peripheral reset. A device reset causes a global peripheral reset.
• By clearing the IRS bit in the I2C mode register (I2CMDR). When the global peripheral reset is
removed, the IRS bit is cleared to 0, keeping the I2C module in the reset state.
31.2.3 I2C Module Data Validity
The data on the SDA must be stable during the high period of the clock. See Figure 31-4. The high and
low state of the data line, the SDA, can only change when the clock signal is low.
Figure 31-4. Bit Transfer on the I2C Bus
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