I2C Control Registers
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SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
31.6.3 I2C Status Register (I2CSTR)
Figure 31-15 and Table 31-7 describe this register.
Figure 31-15. I2C Status Register (I2CSR) [offset = 08h]
15 14 13 12 11 10 9 8
Reserved SDIR NACKSNT BB RSFULL XSMT AAS AD0
R-0 R/W1C-0 R/W1C-0 R-0 R-0 R/W-1 R-0 R-0
7 6 5 4 3 2 1 0
Reserved SCD TXRDY RXRDY ARDY NACK AL
R-0 R/W1C-0 R/W-1 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 31-7. I2C Status Register (I2CSTR) Field Descriptions
Bit Field Value Description
15 Reserved 0 Reads return 0. Writes have no effect.
14 SDIR Slave direction.
Setting this bit to 1 indicates that the I2C slave is a transmitter. Clearing this bit to 0 indicates that
the I2C is a master transmitter/receiver or a slave receiver. This bit is also cleared by the STOP or
START conditions. In DLB mode (in which the configuration should be master-transmitter slave-
receiver), this bit is cleared to 0.
Writing a 1 to this bit will clear it.
0 The I2C is a master transmitter/receiver or a slave receiver.
1 The I2C is a slave transmitter.
13 NACKSNT No acknowledge sent.
This bit is set to 1 to indicate that a no acknowledgement (NACK) has been sent because the
NACKMOD bit was set to 1.
Writing a 1 to this bit will clear it.
0 A NACK has not been sent.
1 A NACK was sent because the NACKMOD was set to 1.
12 BB Bus busy.
This bit indicates the state of the serial bus.
On reception of a START condition or if the I2C detects a low state on I2CSCL, the device sets BB
= 1. If the nIRS is set to 1 during transaction between other I2C devices, the BB bit is set at the first
falling edge of SCL or START condition.
BB is cleared to 0 after the reception of a STOP condition. BB is kept to 0 regardless of the SCL
state when the I2C is in reset (nIRS = 0).
0 The bus is free.
1 The bus is busy.
11 RSFULL Receiver shift full.
This bit is set to 1 to indicate that the receiver has experienced overrun. Overrun occurs when the
receive shift register is full and I2CDRR has not been read since the receive shift register to
I2CDRR transfer. The contents of I2CDRR are not lost. The I2C core logic is holding for I2CDRR
read access. This bit is also set when, in master-repeat-mode, the I2C receives a byte of data.
There is no difference between RXRDY and RSFULL in this case. The I2C master will not continue
the transfer as long as the received data is in the I2CDRR or receive shift register.
RSFULL is cleared when reading the I2CDRR, resetting the I2C (nIRS = 0), or resetting the
device.
0 No overrun has occurred.
1 An overrun has occurred.
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