I2C Control Registers
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SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
Table 31-7. I2C Status Register (I2CSTR) Field Descriptions (continued)
Bit Field Value Description
2 ARDY Register access ready interrupt flag.
This bit is set to 1 when the previously programmed address, data and command has been
performed and the status bit has been updated. The flag is used by the device to indicate that the
I2C registers are ready to be accessed again.
This bit is automatically cleared by hardware when writing data to I2CDXR in transmit mode,
reading data from I2CDRR in receive mode, or setting STT or STP bit. Writing a 1 to this bit
will clear this bit. This bit cannot be cleared by reading the I2CIVR register.
When RM = 0, ARDY is set when I2CCNT is passed 0 if STP register bit has not been set. When
RM = 1, ARDY is set at each byte end.
When FDF = 0, ARDY is asserted after the ACK for the slave address. When FDF = 1, there is no
slave address. Therefore, ARDY is asserted after sending the start condition.
0 Nonrepeat mode, (RM = 0): I2C registers are not ready to be accessed.
Repeat mode (RM = 1): I2C registers are not ready to be accessed.
1 Nonrepeat mode, (RM = 0): ICCNT passes 0 (if STP bit has not been set).
Repeat mode (RM = 1): The end of each byte was transmitted from I2CDXR.
1 NACK No acknowledgement interrupt.
This bit is set to 1 when the master I2C does not receive an acknowledgement from the receiver.
This bit is set only when the I2C has received a no-acknowledge in master mode. This bit is NOT
set by no-acknowledgement after Start byte. In master start byte mode, the first byte (address of all
zeroes) receives a NACK but does not clear the stop bit.
Writing a 1 to this bit or reading the value 0x0002 from I2CIVR will clear this bit.
0 An acknowledge was detected.
1 No acknowledge was detected or the I2C is operating in the general call, even though an
acknowledgement was received. This value clears the STP bit.
0 AL Arbitration lost interrupt flag.
This bit is set to 1 when arbitration has been lost.
Writing a 1 to this bit or reading the value 0x0001 from I2CIVR will clear this bit.
0 No loss of arbitration has been detected.
1 The device in the master transmitter mode senses it has lost an arbitration. This occurs when two
or more transmitters start a transmission almost simultaneously or when the I2C attempts to start a
transfer while BB=1. When this is set to 1 due to arbitration lost, the device becomes a slave
receiver and the MST, STT and STP bits in I2CMDR are cleared to 0.
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