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I2C Control Registers
1789
SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
31.6.8 I2C Slave Address Register (I2CSAR)
The I2C slave address register is a 16-bit memory-mapped register used to specify the address of the
slave device to communicate to on the I2C bus. Figure 31-20 and Table 31-12 describe this register.
Figure 31-20. I2C Slave Address Register (I2CSAR) [offset = 1Ch]
15 10 9 0
Reserved SA
R-0 R/W-3FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-12. I2C Slave Address Register (I2CSAR) Field Descriptions
Bit Field Value Description
15-10 Reserved 0 Reads return 0. Writes have no effect.
9-0 SA 7- or 10-bit programmable slave address.
In either mode, all 10-bits are readable and writable. Bits 7, 8, and 9 should only be used in 10-bit
address mode. Table 31-13 illustrates the correct mode for each bit.
Table 31-13. Correct Mode for SA Bits
Bits Used Mode Value of XA
SA(6–0) 7-bit addressing 0
SA(9–0) 10-bit addressing 1
31.6.9 I2C Data Transmit Register (I2CDXR)
Figure 31-21 and Table 31-14 describe this register.
Figure 31-21. I2C Data Transmit Register (I2CDXR) [offset = 20h]
15 8 7 0
Reserved DATATX
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-14. I2C Data Transmit Register (I2CDXR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 DATATX 0-FFh Transmit data.
Data written to this register will be transmitted on the I2C bus. A write to this register clears the
TXRDY bit and clears code 0x05 from the I2CIVR register.
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