I2C Control Registers
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SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
31.6.6 I2C Data Count Register (I2CCNT)
The I2C data count register is a 16-bit memory-mapped register used to count received or transmitted
data bytes. This register is also used to generate the STOP condition that terminates the transfer after the
counter reaches zero. Figure 31-18 and Table 31-10 describe this register.
Figure 31-18. I2C Data Count Register (I2CCNT) [offset = 14h]
15 0
CNT
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 31-10. I2C Data Count Register (I2CCNT) Field Descriptions
Bit Field Value Description
15-0 CNT Data counter.
This down counter is used to generate a stop condition if a stop condition is specified (STP = 1).
Note: ICCNT is a don’t care when RM is set to 1.
0 The data counter is 65536.
1 The data counter is 1.
31.6.7 I2C Data Receive Register (I2CDRR)
The I2C data receive register is a 16-bit memory-mapped register used by the device to read the received
data. Figure 31-19 and Table 31-11 describe this register.
Figure 31-19. I2C Data Receive Register (I2CDRR) [offset = 18h]
15 8 7 0
Reserved DATARX
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 31-11. I2C Data Receive Register (I2CDRR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 DATARX 0-FFh Receive data.
A read from this register clears the RXRDY bit and clears code 4h from the I2CIVR register.
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