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I2C Control Registers
1799
SPNU563A–March 2018
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Inter-Integrated Circuit (I2C) Module
31.6.22 I2C Data Clear Register (I2CDCLR)
The I2CDCLR register is an alias of the I2CDOUT register. Figure 31-35 and Table 31-31 describe this
register.
Figure 31-35. I2C Data Clear Register (I2CDCLR) [offset = 5Ch]
15 2 1 0
Reserved SDACLR SCLCLR
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-31. I2C Data Clear Register (I2CDSET) Field Descriptions
Bit Field Value Description
15-2 Reserved 0 Reads return 0. Writes have no effect.
1 SDACLR Serial data clear.
This bit is used to clear the SDA GPIO pin.
0 Read: Reads return value of SDAOUT.
Write: No effect.
1 Read: Reads return value of SDAOUT.
Write: SDAOUT is cleared to logic low (0).
0 SCLCLR Serial clock clear.
This bit is used to clear the SCL GPIO pin.
0 Read: Reads return value of SCLOUT.
Write: No effect.
1 Read: Reads return value of SCLOUT.
Write: SCLOUT is cleared to logic low (0).
31.6.23 I2C Pin Open Drain Register (I2CPDR)
Figure 31-36 and Table 31-32 describe this register.
Figure 31-36. I2C Pin Open Drain Register (I2CPDR) [offset = 60h]
15 2 1 0
Reserved SDAPDR SCLPDR
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31-32. I2C Pin Open Drain Register (I2CPDR) Field Descriptions
Bit Field Value Description
15-2 Reserved 0 Reads return 0. Writes have no effect.
1 SDAPDR SDA pin open drain enable.
0 The open drain function is enabled (the output voltage is V
OL
or lower if SDAOUT = 0 and high-
impedance if SDAOUT = 1).
1 The open drain function is disabled (output voltage is V
OL
or lower if SDAOUT = 0; V
OH
or higher if
SDAOUT = 1).
0 SCLPDR SCL pin open drain enable.
0 The open drain function is enabled (the output voltage is V
OL
or lower if SCLOUT = 0 and high-
impedance if SCLOUT = 1).
1 The open drain function is disabled (output voltage is V
OL
or lower if SCLOUT = 0; V
OH
or higher if
SCLOUT = 1).
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