Texas Instruments TMS570LC4357 - Page 18

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18
SPNU563A–March 2018
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Contents
23.6.2 Abbreviations, Encoding Formats and Bits ............................................................... 1062
23.6.3 Instruction Description ....................................................................................... 1065
24 High-End Timer Transfer Unit (HTU) Module....................................................................... 1131
24.1 Overview.................................................................................................................. 1132
24.1.1 Features ........................................................................................................ 1132
24.2 Module Operation ....................................................................................................... 1133
24.2.1 Data Transfers between Main RAM and N2HET RAM................................................... 1135
24.2.2 Arbitration of HTU Elements and Frames.................................................................. 1139
24.2.3 Conditions for Frame Transfer Interruption ................................................................ 1140
24.2.4 HTU Overload and Request Lost Detection ............................................................... 1140
24.2.5 Memory Protection ............................................................................................ 1143
24.2.6 Control Packet RAM Parity Checking ...................................................................... 1143
24.3 Use Cases................................................................................................................ 1145
24.3.1 Example: Single Element Transfer with One Trigger Request.......................................... 1145
24.3.2 Example: Multiple Element Transfer with One Trigger Request ........................................ 1145
24.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields.............................................. 1147
24.4 HTU Control Registers.................................................................................................. 1148
24.4.1 Global Control Register (HTU GC).......................................................................... 1149
24.4.2 Control Packet Enable Register (HTU CPENA)........................................................... 1150
24.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0)..................................................... 1151
24.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1)..................................................... 1152
24.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2)..................................................... 1152
24.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3)..................................................... 1153
24.4.7 Active Control Packet and Error Register (HTU ACPE).................................................. 1153
24.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL)...................................... 1155
24.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS) ................................................ 1156
24.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC) ............................................ 1156
24.4.11 Interrupt Mapping Register (HTU INTMAP) .............................................................. 1157
24.4.12 Interrupt Offset Register 0 (HTU INTOFF0).............................................................. 1158
24.4.13 Interrupt Offset Register 1 (HTU INTOFF1).............................................................. 1159
24.4.14 Buffer Initialization Mode Register (HTU BIM)........................................................... 1160
24.4.15 Request Lost Flag Register (HTU RLOSTFL) ........................................................... 1162
24.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL) ..................................................... 1162
24.4.17 BER Interrupt Flag Register (HTU BERINTFL).......................................................... 1163
24.4.18 Memory Protection 1 Start Address Register (HTU MP1S)............................................ 1164
24.4.19 Memory Protection 1 End Address Register (HTU MP1E)............................................. 1164
24.4.20 Debug Control Register (HTU DCTRL)................................................................... 1165
24.4.21 Watch Point Register (HTU WPR) ........................................................................ 1166
24.4.22 Watch Mask Register (HTU WMR)........................................................................ 1166
24.4.23 Module Identification Register (HTU ID).................................................................. 1167
24.4.24 Parity Control Register (HTU PCR) ....................................................................... 1168
24.4.25 Parity Address Register (HTU PAR) ...................................................................... 1169
24.4.26 Memory Protection Control and Status Register (HTU MPCS)........................................ 1170
24.4.27 Memory Protection Start Address Register 0 (HTU MP0S)............................................ 1173
24.4.28 Memory Protection End Address Register (HTU MP0E) ............................................... 1173
24.5 Double Control Packet Configuration Memory ...................................................................... 1174
24.5.1 Initial Full Address A Register (HTU IFADDRA) .......................................................... 1175
24.5.2 Initial Full Address B Register (HTU IFADDRB) .......................................................... 1175
24.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT) ....................................... 1176
24.5.4 Initial Transfer Count Register (HTU ITCOUNT).......................................................... 1177
24.5.5 Current Full Address A Register (HTU CFADDRA) ...................................................... 1178
24.5.6 Current Full Address B Register (HTU CFADDRB) ...................................................... 1179
24.5.7 Current Frame Count Register (HTU CFCOUNT) ........................................................ 1180