www.ti.com
ePWM Registers
2099
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Enhanced Pulse Width Modulator (ePWM) Module
35.4.7 PWM-Chopper Submodule Register
35.4.7.1 PWM-Chopper Control Register (PCCTL)
Figure 35-90. PWM-Chopper Control Register (PCCTL) [offset = 3Eh]
15 11 10 8
Reserved CHPDUTY
R-0 R/W-0
7 5 4 1 0
CHPFREQ OSHTWTH CHPEN
R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35-50. PWM-Chopper Control Register (PCCTL) Bit Descriptions
Bits Name Value Description
15-11 Reserved 0 Reserved
10-8 CHPDUTY Chopping Clock Duty Cycle.
0 Duty = 1/8 (12.5%)
1h Duty = 2/8 (25.0%)
2h Duty = 3/8 (37.5%)
3h Duty = 4/8 (50.0%)
4h Duty = 5/8 (62.5%)
5h Duty = 6/8 (75.0%)
6h Duty = 7/8 (87.5%)
7h Reserved
7-5 CHPFREQ Chopping Clock Frequency.
0 Divide by 1 (no prescale, = 12.5 MHz at 100 MHz VCLK3)
1h Divide by 2 (6.25 MHz at 100 MHz VCLK3)
2h Divide by 3 (4.16 MHz at 100 MHz VCLK3)
3h Divide by 4 (3.12 MHz at 100 MHz VCLK3)
4h Divide by 5 (2.50 MHz at 100 MHz VCLK3)
5h Divide by 6 (2.08 MHz at 100 MHz VCLK3)
6h Divide by 7 (1.78 MHz at 100 MHz VCLK3)
7h Divide by 8 (1.56 MHz at 100 MHz VCLK3)
To Next Page
Loading...
